Detail publikace

Low-latency AES encryption for High-Frequency Trading on FPGA

CÍBIK, P. RŮŽEK, M. DVOŘÁK, M.

Originální název

Low-latency AES encryption for High-Frequency Trading on FPGA

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper presents a Field Programmable Gate Array (FPGA) powered low--latency solution for secure communication with the stock exchange. It presents architecture design and optimization techniques used to ensure the required security level without impacting the latency, which is the most critical domain in High-Frequency Trading (HFT). The National Stock Exchange of India (NSE) chose Advanced Encryption Standard (AES) with 256 bit key length in Galoise-Counter Mode (GCM) as the encryption algorithm for Non-NEAT Front End (NNF) connections.

Klíčová slova

Field-Programmable Gate Array;FPGA;High-Frequency Trading;HFT;National Stock Exchange of India;NSE;Cryptography;Hardware acceleration;VHDL;Encryption;Decryption;AES;GCM

Autoři

CÍBIK, P.; RŮŽEK, M.; DVOŘÁK, M.

Vydáno

23. 4. 2024

Nakladatel

Brno University of Technology, Faculty of Electronic Engineering and Communication

ISBN

978-80-214-6231-1

Kniha

Proceedings I of the 30th Conference STUDENT EEICT 2024: General papers

Edice

1

Strany od

236

Strany do

240

Strany počet

5

URL

https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdf

BibTex

@inproceedings{BUT188499,
  author="Peter {Cíbik} and Michal {Růžek} and Milan {Dvořák}",
  title="Low-latency AES encryption for High-Frequency Trading on FPGA",
  booktitle="Proceedings I of the 30th Conference STUDENT EEICT 2024: General papers",
  year="2024",
  series="1",
  pages="236--240",
  publisher="Brno University of Technology, Faculty of Electronic Engineering and Communication",
  isbn="978-80-214-6231-1",
  url="https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdf"
}