Detail publikace

Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

KUBÁNEK, D. SHADRIN, A. ŠEDA, P. DVOŘÁK, J. JEŘÁBEK, J. KLEDROWETZ, V. CHRISTIE, C. FREEBORN, T. USHAKOV, P.

Originální název

Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Typ

článek v časopise ve Web of Science, Jimp

Jazyk

angličtina

Originální abstrakt

The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.

Klíčová slova

distributed element;fractional-order element;fractor;genetic algorithm;MOS transistor

Autoři

KUBÁNEK, D.; SHADRIN, A.; ŠEDA, P.; DVOŘÁK, J.; JEŘÁBEK, J.; KLEDROWETZ, V.; CHRISTIE, C.; FREEBORN, T.; USHAKOV, P.

Vydáno

27. 4. 2025

Nakladatel

Springer Nature

ISSN

2045-2322

Periodikum

Scientific Reports

Ročník

15

Číslo

4

Stát

Spojené království Velké Británie a Severního Irska

Strany počet

18

URL

https://link.springer.com/article/10.1038/s41598-025-96539-w

Plný text v Digitální knihovně

http://hdl.handle.net/11012/251028

BibTex

@article{BUT197765,
  author="David {Kubánek} and Aleksandr {Shadrin} and Pavel {Šeda} and Jan {Dvořák} and Jan {Jeřábek} and Vilém {Kledrowetz} and Cole {Christie} and Todd {Freeborn} and Peter A. {Ushakov}",
  title="Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices",
  journal="Scientific Reports",
  year="2025",
  volume="15",
  number="4",
  pages="18",
  doi="10.1038/s41598-025-96539-w",
  issn="2045-2322",
  url="https://link.springer.com/article/10.1038/s41598-025-96539-w"
}